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24-Output PWM LED Drivers
for Message Boards
HOST
MAX6974/MAX6975
1
MAX6974/MAX6975
2
MAX6974/MAX6975
3
CLKO
DOUT
LOADO
CLK0
D0
LOAD0
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLK1
D1
LOAD1
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLK2
D2
LOAD2
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLK3
D3
LOAD3
LOADI
DIN
CLKI
Figure 8. Example Showing Three-Device Cascade Connection Scheme with the Interconnecting Nodes Labeled for Clarity
DATA: CALDAC DATA 1
DATA: CALDAC DATA 2
B CALDAC
G CALDAC
G CALDAC
B CALDAC
G CALDAC
R CALDAC
1
LOADI
DIN
CLKI
0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUOUS)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 9. Timing Example Showing CALDAC Data Set for the First Two Cascaded Devices
Serial-Interface Cascade Timing
The MAX6974/MAX6975 serial-interface protocol timing
CLK0
is simplified by the guaranteed setup and hold charac-
D0
HEADER 1
3 BYTES 1
3 BYTES 2
3 BYTES 3 T
IDLE
teristics of the outputs from one device driving the
inputs of another. An example of a cascade of three
D1
25 CLOCKS
HEADER 2
3 BYTES 2
3 BYTES 3
T
IDLE
MAX6974/MAX6975 devices is shown in Figure 8.
Example of Serial-Interface
D2
D3
25 CLOCKS
HEADER 3
25 CLOCKS
3 BYTES 3
HEADER 4
T IDLE
T IDLE
Cascade Timing
The basic timing of a MAX6974/MAX6975 cascaded
chain of three devices demonstrates the principle that
applies to any number of cascaded devices. The first
device connected to the host transmitter is referenced
as 1, and the remaining devices are referenced as 2
and 3. Device 3 outputs connect to the host for commu-
nicating diagnostic and fault counter data.
The first MAX6974/MAX6975, device 1, receives the
header and captures the first set of data bits. The
number of captured bits is determined by the command
given in the header. A timing example of the data trans-
fer for the Load CALDAC command is shown in Figure
9. Device 1 does not send the captured data out on
DOUT. Instead, device 1 sends out a new header 25
clock cycles after the reception of the first header bit on
DIN. The data flow on each interconnect node is shown
in Figure 10.
Figure 10. Data Cascading Example for 24-Bit Data Words
After capturing the first data set, device 1 transmits all
following data segments and the optional tail segment
on DOUT, delayed by one CLKI cycle. Device 2
receives the new header from device 1, followed by
data that now begins with device 2’s data set. Device 2
repeats the same process as described above; captur-
ing the first data set received, appending a new head-
er, and passing all subsequent data out DOUT to the
next device 3. Device 3 captures the last data set and
transmits a header followed by the tail segment. The
last header and tail segments are clocked back into the
host receiver. The header received by the host contains
the updated fault counter data. The tail data bit pattern
can be compared to the tail data originally transmitted
by the host for data integrity check.
______________________________________________________________________________________
19
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